A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells

TL;DR

This paper introduces a low-power cache design that reduces leakage in 6T SRAM cells by serially interconnecting adjacent cells, requiring minimal modifications to existing cache structures.

Contribution

It proposes a novel serial interconnection architecture for 6T SRAM cache cells to lower leakage power without increasing cell complexity.

Findings

Leakage power is significantly reduced compared to conventional schemes.

The architecture maintains standard 6T SRAM cell design.

Simulation confirms effectiveness in leakage suppression.

Abstract

This paper presents a low-power cache architecture based on the series interconnection of conventional 6-transistor static random-access memory (6T SRAM) cells. The proposed approach aims to reduce leakage power in SRAM-based cache memories without increasing the transistor count of the memory cell itself. In the proposed architecture, adjacent cells within a column are reconfigured in a serial topology, thereby exploiting the stacking effect to suppress leakage current, particularly during hold operation. This architectural modification requires corresponding changes to the addressing and sensing structure of the cache, including adjustments to the column organization and readout path. To evaluate the proposed method, transient simulations were carried out using Keysight ADS. The simulation results show that the proposed architecture reduces leakage power compared with the conventional SRAM interconnection scheme while preserving the use of standard 6T SRAM cells.