Potentials and Pitfalls of Applying Federated Learning in Hardware Assurance
Gijung Lee, Wavid Bowman, Olivia Dizon-Paradis, Reiner Dizon-Paradis, Ronald Wilson, Damon Woodard, Domenic Forte

TL;DR
This paper explores the use of federated learning for hardware assurance, demonstrating its benefits in collaborative model training and revealing significant privacy vulnerabilities like gradient inversion attacks.
Contribution
It is the first to apply federated learning to hardware assurance, showing performance improvements and exposing critical privacy risks in this domain.
Findings
FL outperforms single-client learning in reverse engineering segmentation tasks.
Increasing clients improves FL model performance.
Gradient inversion attacks can recover sensitive SEM images in FL, exposing IP.
Abstract
As microelectronics flourish and outsourcing of the design and manufacturing stages of integrated circuits (ICs) and printed circuit boards (PCBs) becomes the norm, microelectronics stakeholders must also confront a new wave of security challenges, including the threats posed by hardware Trojans, counterfeit electronics, and reverse engineering attacks. Traditional detection and prevention methods like testing and side-channel analysis have limitations in reliability and scalability. Automated reverse engineering by deep learning (DL) models is a foolproof approach to hardware assurance, but faces challenges due to limited data. By pooling data from different stakeholders (competitors in industry, governments, etc.), DL models can be more effectively trained but privacy of intellectual property (IP) is a significant concern. Federated Learning (FL) has been proposed as a potential…
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