Toward designing workload-aware Surface Code Architectures

TL;DR

This paper introduces a workload-aware surface code architecture that balances qubit accessibility and density, optimizing quantum error correction for multiple concurrent programs.

Contribution

It proposes a novel surface code layout with workload-driven placement and reconfigurable optimization, enhancing efficiency and flexibility in fault-tolerant quantum computing.

Findings

Reduces data tile count by up to 21%.

Achieves up to 90% efficiency with 10 concurrent programs.

Maintains near-optimal cycles per instruction.

Abstract

Practical quantum advantage is expected to depend on fault-tolerant quantum computing, although the architectural overhead needed to support fault tolerance is still extremely high. Prior FTQC designs generally emphasize either fast logical-qubit accessibility at the cost of significant qubit overhead, or high logical-qubit density at the cost of added workload latency. We propose an architecture that balances these competing objectives by placing surface-code patches around an ancilla-centric region, which yields nearly uniform ancilla access for all data qubits. Building on this design, we introduce a new workload-driven placement method that uses the $T$-gate profile of an application to determine an effective floorplan. We further provide a reconfigurable optimization for reducing the latency of $Y$-gate measurements on a per-workload basis. To improve flexibility, we also study concurrent execution of multiple programs on the same architecture. Numerical evaluation indicates that our approach keeps cycles per instruction near the optimal regime while reducing the number of required data tiles by up to $\sim21\%$, and achieves up to $\sim90\%$ efficiency when running 10 programs concurrently.