Silicon Aware Neural Networks

TL;DR

This paper introduces a method to map Differentiable Logic Gate Networks (DLGNs) directly onto silicon, optimizing for area and power, and demonstrates a high-speed, low-power MNIST classifier in simulation.

Contribution

It presents a novel approach to convert trained DLGNs into silicon circuits with optimized area and power, including a full layout and power analysis in a standard process.

Findings

Achieved 97% accuracy on MNIST with DLGN in simulation.

Demonstrated a DLGN circuit performing 41.8 million classifications per second.

Power consumption of the silicon implementation is 83.88 mW.

Abstract

Recent work in the machine learning literature has demonstrated that deep learning can train neural networks made of discrete logic gate functions to perform simple image classification tasks at very high speeds on CPU, GPU and FPGA platforms. By virtue of being formed by discrete logic gates, these Differentiable Logic Gate Networks (DLGNs) lend themselves naturally to implementation in custom silicon - in this work we present a method to map DLGNs in a one-to-one fashion to a digital CMOS standard cell library by converting the trained model to a gate-level netlist. We also propose a novel loss function whereby the DLGN can optimize the area, and indirectly power consumption, of the resulting circuit by minimizing the expected area per neuron based on the area of the standard cells in the target standard cell library. Finally, we also show for the first time an implementation of a DLGN as a silicon circuit in simulation, performing layout of a DLGN in the SkyWater 130nm process as a custom hard macro using a Cadence standard cell library and performing post-layout power analysis. We find that our custom macro can perform classification on MNIST with 97% accuracy 41.8 million times a second at a power consumption of 83.88 mW.