Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging
Dinithi Jayasuriya, Aravind Saravanan, Nilesh Ahuja, Amanda Rios, Amit Trivedi

TL;DR
This paper introduces a structural verification approach that enforces correctness of LLM-generated EDA scripts before execution, significantly improving reliability and reducing tool calls without relying on iterative debugging.
Contribution
It presents a verifier-guided synthesis framework that enforces structural dependencies through graph-conditioned retrieval and staged verification, eliminating the need for tool-in-the-loop debugging.
Findings
Pass rate for single-step tasks increased from 73-76% to 82.5%.
Multi-step task success rate improved from 30% to 84%.
Verifier false positives reduced from 20% to 6.7%, with precision up to 93.3%.
Abstract
Large language models (LLMs) have enabled natural-language-driven automation of electronic design automation (EDA) workflows, but reliable execution of generated scripts remains a fundamental challenge. In LLM-based EDA tasks, failures arise not from syntax errors but from violations of implicit structural dependencies over design objects, including invalid acquisition paths, missing prerequisites, and incompatible API usage. Existing approaches address these failures through tool-in-the-loop debugging, repeatedly executing and repairing programs using runtime feedback. While effective, this paradigm couples correctness to repeated tool invocation, leading to high latency and poor scalability in multi-step settings. We propose to eliminate tool-in-the-loop debugging by enforcing structural correctness prior to execution. Each task is represented as a structural dependency graph that…
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