Enabling AI ASICs for Zero Knowledge Proof

TL;DR

MORPH is a novel framework that reformulates zero-knowledge proof kernels to leverage AI ASICs like TPUs, achieving significant throughput improvements by hardware-aware optimizations.

Contribution

It introduces a hardware-aware complexity model and new kernel transformations to optimize ZKP computations on AI ASICs, enabling higher throughput and efficiency.

Findings

Up to 10x higher throughput on NTT with TPUv6e8.

Achieves comparable throughput on MSM to state-of-the-art GZKP.

Demonstrates effective hardware-aware kernel reformulation for ZKP.

Abstract

Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH.