AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator

TL;DR

AccelCIM presents a systematic framework for exploring dataflows in SRAM-based compute-in-memory accelerators, optimizing DNN performance and energy efficiency by addressing macro configuration and organization.

Contribution

It introduces a comprehensive dataflow design space and rigorous evaluation methodology for SRAM CIM accelerators, enabling better design choices for large DNN models.

Findings

Design space exploration reveals optimal macro configurations.

Cycle-accurate simulation provides detailed performance insights.

Application to LLMs demonstrates practical benefits.

Abstract

SRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators.