From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
Weimin Fu, Zeng Wang, Minghao Shao, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri, Muhammad Shafique, Xiaolong Guo

TL;DR
This paper investigates how the choice of intermediate representations (IRs) impacts the success of LLM-driven hardware design for FPGAs, revealing the representation bottleneck as a key factor.
Contribution
It demonstrates that IR choice dominates end-to-end success in LLM-based hardware synthesis, highlighting the importance of IR selection over model improvements.
Findings
Simulation pass rates vary from 3% to 88% across IRs.
Within a single IR, model performance varies less than 1.25x.
LLM designs can outperform reference solutions in FPGA pass rates due to size constraints.
Abstract
Edge applications increasingly demand custom hardware, yet Field-Programmable Gate Array (FPGA) design requires expertise that domain engineers lack. Large Language Models (LLMs) promise to bridge this gap through zero-knowledge hardware programming, where users describe circuits in natural language and an LLM compiles them to a hardware intermediate representation (IR) targeting silicon. Modeling this flow as a cascade of binary filters, this work demonstrates that IR choice, not model choice, is the dominant factor governing end-to-end success, a phenomenon termed the representation bottleneck. An evaluation of three frontier LLMs across six IRs spanning Verilog, VHDL, Chisel, Bluespec, PyMTL3, and HLS C on 202 tasks through a pipeline of compilation, simulation, FPGA synthesis on a Lattice iCE40UP5K, and LLM-based repair shows that simulation pass rates range from 3% to 88% across…
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