SAAP: An Efficient Spatial-Aware Analytic Partitioning Algorithm of VLSI Netlists for Parallel Routing

TL;DR

SAAP is a novel spatial-aware partitioning algorithm for VLSI netlists that enforces hard spatial constraints and significantly reduces cut sizes for improved parallel routing.

Contribution

It introduces an analytic boundary modeling and simulated annealing approach to generate spatially continuous partitions considering placement data.

Findings

SAAP achieves several to dozens of times smaller cut sizes than previous methods.

It produces more spatially continuous partitions that are timing-friendly.

The algorithm is efficient and suitable for large, complex VLSI designs.

Abstract

As VLSI designs grow in complexity, partitioning is widely adopted to accelerate physical design through parallel computing. However, traditional hypergraph partitioning methods often degrade in performance when applied to 2D layouts due to spatial constraints. For routers with post-placement locations, a spatial-aware partitioning method fully utilizing placement data is preferable. Existing works can only consider soft spatial constraints, leading to a scattered distribution in one partition. We propose SAAP, an analytic partitioning algorithm enforcing hard spatial constraints while efficiently minimizing cut sizes. It includes analytic boundary modeling with regularity-guided simulated annealing and region embedding. Given placed netlists, it generates timing-friendly k-way spatially continuous partitions for parallel routing. Experiments show that it can quickly provide several to dozens of times smaller spatial cut sizes than previous state-of-the-art, with better spatial continuity.