Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation

TL;DR

This paper introduces a workflow utilizing multi-agent models to generate testbenches, enabling efficient fine-tuning of LLMs for Verilog code generation with limited data, achieving competitive results on the VerilogEval v2 benchmark.

Contribution

It presents a novel multi-agent testbench generation approach that enhances LLM fine-tuning for HDL synthesis with minimal training data.

Findings

Achieves performance comparable to state-of-the-art on VerilogEval v2

Uses less training data than existing methods

Automates testbench creation for HDL code generation

Abstract

Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification.