CMOS-integrated superparamagnetic tunnel junction-based p-bit

TL;DR

This paper demonstrates the integration of superparamagnetic tunnel junctions with CMOS technology to create a scalable, CMOS-compatible probabilistic bit (p-bit) for probabilistic computing applications.

Contribution

It provides experimental validation of CMOS-integrated sMTJ-based p-bits, showing their potential for scalable probabilistic hardware.

Findings

sMTJ resistance fluctuations produce tunable digital outputs

Demonstrated CMOS-compatible integration of sMTJs

Established feasibility for scalable probabilistic circuits

Abstract

Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.