TOPCELL: Topology Optimization of Standard Cell via LLMs

TL;DR

TOPCELL leverages Large Language Models to efficiently optimize transistor topologies in standard cell design, significantly reducing computation time while maintaining high layout quality.

Contribution

It introduces a scalable LLM-based framework for topology exploration, outperforming traditional methods in speed and quality for advanced node design.

Findings

Outperforms foundation models in discovering routable topologies

Achieves 85.91x speedup over exhaustive solvers

Maintains layout quality comparable to exhaustive methods

Abstract

Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup.