An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems

TL;DR

This paper introduces a custom ASIC that digitally emulates oscillator-based Ising/Potts machines, achieving high accuracy and efficiency for solving complex combinatorial optimization problems.

Contribution

It presents a scalable, digital ASIC architecture with direct interconnections for emulating OIM/OPM dynamics, overcoming analog limitations and improving performance.

Findings

Achieves 97-100% maximum accuracy on benchmark problems.

Demonstrates significant speed and energy improvements over general-purpose platforms.

Prototyped a 20x20 processing element array with high scalability.

Abstract

Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms, demonstrating the viability of algorithmically codesigned ASICs.