A Modular and T-Gate Efficient Architecture for Quantum Leading-Zero/One Counter

TL;DR

This paper introduces a scalable, resource-efficient quantum leading-zero/one counter architecture that reduces T-gate count and depth, enhancing quantum arithmetic performance.

Contribution

It presents a modular, polymorphic design reformulating counting into conditional bit-flips, with variants that optimize T-gate resources and scalability.

Findings

Reduces T-count by 40% compared to existing designs.

Achieves 60% reduction in T-depth over state-of-the-art.

Supports seamless scalability to any bit-width without re-tuning.

Abstract

The Quantum Leading-Zero/One Counter (QLZOC) is a fundamental component in quantum arithmetic, playing a critical role in normalization, floating-point units, dynamic range scaling, and logarithmic approximations. Conventional designs primarily rely on direct Boolean-to-quantum mapping, which results in inefficient resource utilization such as irregular gate growth and width-dependent resource overhead. In this work, we propose a scalable, modular, and resource efficient architecture for QLZOC by reformulating the counting process into a sequence of systematic conditional bit-flip operations. Moreover, our design achieves functional polymorphism so that the same design can be easily toggled between zero and one detection, while ensuring seamless scalability to any bit-width without manual re-tuning. We further introduce a Parallel QLZOC (PQLZOC) variant and a Fan-Out optimized (FO-PQLZOC) design. In this work, we evaluate resource efficiency based on the classic criteria about T gates, including the number of total T gates being used (T-count) and the number of sequential T gate layers (T-depth). By exploiting the properties of all-zero/one qubit blocks and a hierarchical merge strategy, the proposed FO-PQLZOC reduces the T-depth from O(m) to O(log m), where m is the input size. Comparative analysis demonstrates that our optimized architecture achieves a 40% reduction in T-count and a 60% reduction in T-depth over state-of-the-art designs, providing a high-performance, T-gate efficient solution for general-purpose quantum arithmetic processors.