A $\boldsymbol{2d \times d \times d}$ Spacetime Volume Implementation of a Logical S Gate in the Surface Code
Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki

TL;DR
This paper introduces a new circuit-level implementation of the logical S gate in the surface code that reduces the spacetime volume from traditional methods, with comparable logical error rates at large code distances.
Contribution
It provides the first circuit-level implementation of a reduced-volume S gate protocol and refines it for nearest-neighbor gates, enabling better fault-tolerance analysis.
Findings
The proposed method reduces the spacetime volume to 2d × d × d.
Logical error rates are comparable to existing methods at large code distances.
The new protocol is feasible with standard syndrome extraction circuits.
Abstract
The logical S gate implemented via twist defect braiding in the surface code is one of the major sources of overhead in fault-tolerant quantum computing, since an S-gate correction is required in every logical T-gate teleportation. Existing logical S-gate implementations require spacetime volumes of \(2d \times 2d \times d\) or \(2d \times 1.5d \times d\), where is the code distance of the surface code. To the best of our knowledge, their circuit-level implementations have not yet been shown, hindering quantitative comparisons of fault distances and logical error rates. In this work, we provide these missing circuit-level implementations. Additionally, we propose a novel twist defect braiding protocol that reduces the spacetime volume to \(2d \times d \times d\). First, we construct an implementation of the proposed method using constant-length non-local gates, and then refine it to…
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