DTCO Exploration of NOR-Type IGZO FeFETs for Read-Dominated Memories

TL;DR

This paper evaluates NOR-type IGZO FeFETs for read-centric AI inference, demonstrating scalable bitcell design, addressing sneak current issues, and analyzing 3D stacking implications for storage-class memories.

Contribution

It introduces a design-technology cooptimization approach for IGZO FeFETs, highlighting scalability, read performance, and sneak current mitigation strategies.

Findings

Achieved 10-A SRAM-equivalent area with 7-nm nodes

Identified sensing margin penalties due to sneak current

Analyzed 3D stacking density limits from sneak current effects

Abstract

InGaZnO (IGZO) channel FeFETs have attracted notable interest thanks to their advances in endurance. This work evaluates the viability of NOR-type IGZO FeFETs for readcentric AI inference workloads via design-technology cooptimization (DTCO). We demonstrate the cross-node bitcell footprint scalability of back-end-of-line (BEOL) IGZO FeFETs capable of delivering 10-A SRAM-equivalent area (0.016 um2) with 7-nm ground rules and reaching sub-5 ns random access latency despite writability challenges. We further identify the sensing margin penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state Vt, which requires positive-Vt engineering in order to eliminate the unwanted negative voltage read inhibition - for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3D FeNOR for storage-class memories (SCMs), with the 3D stacking density limited by additional sneak current from neighbor channel shunting.