Cross-Layer Co-Optimized LSTM Accelerator for Real-Time Gait Analysis

TL;DR

This paper introduces a novel cross-layer co-optimized LSTM accelerator tailored for real-time gait analysis on ASICs, optimizing for performance, power, and area with comprehensive design exploration.

Contribution

It presents the first ASIC-based LSTM accelerator specifically designed for gait analysis, including software-hardware co-optimization and layout exploration.

Findings

Achieves 4.05x faster gait abnormality detection than application requirements.

Optimized for high accuracy with a 0.325 mm^2 die size in 65 nm technology.

Alternative design reduces area by 15.4% with slightly lower accuracy.

Abstract

Long Short-Term Memory (LSTM) neural networks have penetrated healthcare applications where real-time requirements and edge computing capabilities are essential. Gait analysis that detects abnormal steps to prevent patients from falling is a prominent problem for such applications. Given the extremely stringent design requirements in performance, power dissipation, and area, an Application-Specific Integrated Circuit (ASIC) enables an efficient real-time exploitation of LSTMs for gait analysis, achieving high accuracy. To the best of our knowledge, this work presents the first cross-layer co-optimized LSTM accelerator for real-time gait analysis, targeting an ASIC design. We conduct a comprehensive design space exploration from software down to layout design. We carry out a bit-width optimization at the software level with hardware-aware quantization to reduce the hardware complexity, explore various designs at the register-transfer level, and generate alternative layouts to find efficient realizations of the LSTM accelerator in terms of hardware complexity and accuracy. The physical synthesis results show that, using the 65 nm technology, the die size of the accelerator's layout optimized for the highest accuracy is 0.325 mm^2, while the alternative design optimized for hardware complexity with a slightly lower accuracy occupies 15.4% smaller area. Moreover, the designed accelerators achieve accurate gait abnormality detection 4.05x faster than the given application requirement.