Building reliable 3D photonic integrated circuits and cavities at the wafer scale
Yuhao Huang, Yunqi Fu, Yu Xia, Yuemin Li, Zheng Li, Yaoran Huang, Zhaoting Geng, Mingfei Liu, Chao Xiang

TL;DR
This paper introduces a scalable fabrication method for reliable 3D photonic integrated circuits with low loss and high uniformity, enabling advanced optical devices and systems.
Contribution
It presents a novel etch-back assisted chemical mechanical polishing process and a $ppa$-engineered taper design to improve wafer-scale 3D PIC fabrication.
Findings
Achieved wafer-scale uniform spacer layer using E-CMP.
Demonstrated a $ppa$-engineered taper with 75% higher reliability.
Realized 3D PICs with low propagation loss and low 3D transition loss.
Abstract
Three-dimensional (3D) photonic integrated circuits (PIC) are emerging as an indispensable scheme for high density and multifunctional photonic systems. However, the wafer-scale scaling of PICs towards a 3D configuration is constrained by two key factors: (i) the trade-off between inter-layer taper efficiency and footprint, and (ii) wafer-scale uniformity of inter-layer transition loss. In this work, we introduce etch-back assisted chemical mechanical polishing (E-CMP) to achieve high wafer-scale uniformity of the spacer layer. Moreover, we break the efficiency-footprint trade-off by demonstrating a novel -engineered taper, achieving a reliability metric that is 75\% higher than the traditional linearly tapered structure. Building on these design and fabrication developments, we enable reliable 3D PICs with typical loss of 0.077 and 0.068 dB/cm on two silicon nitride (SiN)…
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