EPAC: The Last Dance

TL;DR

EPAC is a multi-tile RISC-V accelerator chip developed in Europe for HPC workloads, integrating vector, many-core, and variable-precision compute tiles, and successfully validated in GF22FDX technology.

Contribution

This paper introduces EPAC, a novel multi-tile RISC-V accelerator chip designed for HPC, highlighting its architecture, integration, and validation within a European collaborative effort.

Findings

Successfully taped out and validated all major IP blocks.

Integrated three specialized RISC-V compute tiles for diverse workloads.

Provided insights into multi-partner chip design and implementation processes.

Abstract

This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe.