Multiplexed cryo-CMOS control of an isolated double quantum dot

TL;DR

This paper demonstrates that multiplexed cryo-CMOS control can reliably operate a silicon double quantum dot at 0.5K, enabling scalable, stable, and rapid control of quantum dot charge states for quantum computing.

Contribution

It provides the first experimental validation of sample-and-hold multiplexed control for quantum dots at cryogenic temperatures, compatible with static biasing and pulsing.

Findings

Successfully biased a silicon double quantum dot at 0.5K using multiplexed control.

Achieved deterministic loading and stable access to multiple charge configurations.

Resolved single-electron tunneling events and stochastic switching during pulsing.

Abstract

Scalable spin-based quantum computing demands precise and stable control of a large number of gate-defined quantum dots while minimizing wiring complexity and thermal load. Control architectures based on sample-and-hold (SH) multiplexing techniques offer a promising solution by enabling sequential programming of several gate voltages using a limited number of input lines. However, the compatibility of such dynamic voltage refreshing with the stringent stability, noise, and speed requirements of quantum dot operation is an active subject of study. Here we experimentally demonstrate that a multiplexing cryo-CMOS circuit can reliably bias a silicon double quantum dot (DQD) at 0.5K. Exploiting the isolated regime, we show deterministic loading and isolation of four electrons and stable access to all five charge configurations from (4,0) to (0,4), despite the sequential voltage refreshing. We further demonstrate rapid voltage pulsing across an inter-dot transition, resolving single-electron tunneling events and stochastic switching at the (1,3)-(0,4) transition. These results confirm that SH-based multiplexed control is compatible with both static biasing and pulsing of isolated quantum dots, representing an important milestone toward scalable cryogenic control architectures for large-scale spin-qubit processors.