Automated SVA Generation with LLMs
Lik Tung Fu, Qihang Wang, Shaokai Ren, Mengli Zhang, Sichao Yang, Jun Liu, Xi Wang

TL;DR
This paper introduces SVA Generator, a data-centric framework that translates natural-language SVA descriptions into executable SVAs, significantly improving semantic correctness over general LLMs through structured validation and benchmarking.
Contribution
It presents a novel, data-driven approach with a structured evaluation benchmark for reliable, semantics-preserving SVA generation using LLMs.
Findings
SVA Generator achieves higher semantic equivalence rates than general LLMs.
The framework maintains comparable syntax pass rates across difficulty tiers.
Depth-stratified benchmarking reveals the importance of high-fidelity data for semantic accuracy.
Abstract
Functional verification remains a dominant cost in modern IC development, and SystemVerilog Assertions (SVAs) are critical for simulation-based monitoring and formal property checking. However, writing SVAs by hand is time-consuming and error-prone. Directly prompting general-purpose large language models (LLMs) is also unreliable: the generated properties are often syntactically invalid or semantically incorrect, and the problem is exacerbated by scarce, high-quality domain training data. We present SVA Generator, a data-centric framework that translates natural-language SVA Descriptions (SVADs) into executable SVAs. It uses AST-grounded constraint injection and an automated supervision pipeline that enforces structural consistency and reduces hallucinations via de-duplication and constraint checks. To enable rigorous evaluation, we introduce a benchmark suite stratified by AST depth…
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