From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU

TL;DR

This paper conducts an empirical reliability study of BFP-based NPUs, revealing vulnerabilities and proposing a fault-tolerant microarchitecture with minimal performance and hardware overhead.

Contribution

It introduces the first detailed fault analysis of BFP NPUs and proposes a novel microarchitecture that enhances reliability with low overhead.

Findings

Heterogeneous vulnerabilities in BFP NPUs identified through fault injection.

Conventional end-to-end checks are ineffective under nonlinear block scaling.

Proposed microarchitecture achieves near-dual redundancy reliability with minimal overhead.

Abstract

Block Floating-Point (BFP) is emerging as an attractive data format for edge Neural Processing Units (NPUs), combining wide dynamic range with high hardware efficiency. However, its behavior under hardware faults and suitability for safety-critical deployments remain underexplored. Here, we present the first in-depth empirical reliability study of BFP-based NPUs. Using RTL-level fault injection on NPUs, our bit- and path-level analysis reveals pronounced heterogeneous vulnerabilities and shows conventional end-to-end check becomes ineffective under nonlinear block scaling. Guided by these insights, we design a fault-tolerant BFP-based NPU microarchitecture that aligns the BFP computational semantics with reliability constraints. The design uses a row/column-wise blocking strategy to decouple the fixed-point mantissa computations from the scalar exponent path, and introduces ultra-lightweight protection mechanisms for each. Experimental results demonstrate our design achieves near-dual modular redundancy reliability with only $3.55\%$ geometric mean performance overhead and less than $2\%$ hardware cost.