Quantum Error Mitigation Strategies for Variational PDE-Constrained Circuits on Noisy Hardware
Prasad Nimantha Madusanka Ukwatta Hewage, Midhun Chakkravarthy, Ruvan Kumara Abeysekara

TL;DR
This paper systematically evaluates noise mitigation strategies for variational quantum circuits solving PDEs on noisy hardware, demonstrating the effectiveness of zero-noise extrapolation and the inherent noise resilience of physics-constrained circuits.
Contribution
It provides a comprehensive analysis of error mitigation techniques and reveals that physics constraints improve noise resilience in variational PDE solvers on NISQ devices.
Findings
Zero-noise extrapolation reduces error by up to 96%.
Physics-constrained circuits maintain higher fidelity under noise.
Probabilistic error cancellation is effective but has high sampling costs.
Abstract
Variational quantum circuits (VQCs) solving partial differential equations (PDEs) on near-term quantum hardware face a critical challenge: hardware noise degrades solution fidelity and disrupts convergence. We present a systematic study of three noise channels; depolarizing, amplitude damping, and bit-flip on VQCs constrained by PDE residual loss functions for the heat equation, Burgers' equation, and the Saint-Venant shallow water equations. We benchmark three error mitigation strategies: zero-noise extrapolation (ZNE) via Richardson polynomial fitting, probabilistic error cancellation (PEC), and measurement error mitigation through inverse confusion matrices. Our numerical experiments on 6-qubit, 4-layer circuits demonstrate that ZNE reduces absolute error by 82-96% at low noise (p = 0.001), with effectiveness degrading gracefully at higher noise strengths. We prove analytically and…
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