Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits

TL;DR

This paper introduces a resist-free silicon trench method for fabricating Josephson junctions in superconducting qubits, improving surface quality and process scalability.

Contribution

The authors present a CMOS-compatible, resist-free fabrication technique using etched silicon trenches for Josephson junctions in superconducting qubits.

Findings

Median energy relaxation times up to 184 microseconds.

Minimal contamination at substrate-metal interface.

Stable relaxation times over 35 hours.

Abstract

Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.