Interferences within a certifiable design methodology for high-performance multi-core platforms

TL;DR

This paper presents a multi-level methodology combining hardware, software, and system techniques to analyze and mitigate resource interference in high-performance multi-core platforms for safety-critical applications.

Contribution

It introduces an integrated approach that combines formal hardware modeling, machine learning, compiler transformations, and system constraints to reduce interference and enhance predictability.

Findings

Reduced memory interference in multi-core systems.

Improved system predictability for safety-critical domains.

Facilitated certification process through interference mitigation.

Abstract

The adoption of high-performance multi-core platforms in avionics and automotive systems introduces significant challenges in ensuring predictable execution, primarily due to shared resource interferences. Many existing approaches study interference from a single angle-for example, through hardware-level analysis or by monitoring software execution. However, no single abstraction level is sufficient on its own. Hardware behavior, program structure, and system configuration all interact, and a complete view is needed to understand where interferences come from and how to reduce them. In this paper, we present a methodology that brings together several tools that operate at different abstraction levels. At the lowest level, PHYLOG provides a formal model of the hardware and identifies possible interference channels using micro-architectural transactions. At the program level, machine learning analysis locates the exact parts of the code that are most sensitive to shared-resource contention. At the compilation level, MLIR-based transformations use this information to reshape memory access patterns and reduce pressure on shared resources. Finally, at the system level, Linux cgroups enforce static execution constraints to prevent highly interfering tasks from running together. The goal of our approach is to reduce memory interference and improve the system's predictability, thereby easing the certification process of multi-core systems in safety-critical domains.