From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
Yonghao Wang, Hongqin Lyu, Boling Chen, MinYang Bao, Wenchao Ding, Feng Gu, Zhiteng Chao, Jianan Mu, Kan Shi, Tiancheng Wang, Huawei Li

TL;DR
This paper introduces AgileAssert, a framework that leverages critical signal identification and RTL slicing to generate targeted assertions with LLMs, significantly improving verification efficiency and coverage.
Contribution
It presents a novel key signal-driven assertion generation method that reduces verification cost and enhances coverage by focusing on impactful signals and precise RTL slicing.
Findings
Achieves 66.68% reduction in assertions on average
Reduces input token consumption by 64%
Improves error detection rate with fewer assertions in mutation testing
Abstract
Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-based assertion generation methods typically pursue indiscriminate verification, aiming for maximal coverage without considering signal criticality, whereas industrial practice demands maximizing coverage with minimal verification cost. Consequently, identifying signals that have the greatest impact on design functionality and error propagation-enabling a shift from indiscriminate to targeted verification-remains a key challenge. To address this, we propose AgileAssert, a key signal-driven assertion generation framework that constructs RTL semantic graphs and identifies the top-K critical signals via a hybrid scoring and selection mechanism, followed by structure-aware RTL slicing to provide the LLM with…
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