Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing

TL;DR

This paper critically analyzes digital neuromorphic processors, revealing that on-chip memory systems still pose significant energy and area challenges, creating a new memory wall that hampers their efficiency.

Contribution

It provides a detailed critique of current memory architectures in neuromorphic computing and suggests future research directions to address memory bottlenecks.

Findings

On-chip memory consumes significant area and energy.

Memory wall persists despite neuromorphic design efforts.

Emerging memory technologies like STT-MRAM still face challenges.

Abstract

The rapid advancement of neuromorphic technology aims to address the memory wall challenge inherent in conventional von Neumann architectures. This paper critically examines current digital neuromorphic processors and their strategies to mitigate this bottleneck. While designed to bring computation closer to memory through distributed architectures, our findings indicate that on-chip memory systems, including SRAM and emerging technologies like STT-MRAM, have become significant consumers of area and energy, leading to a new memory wall. Through an analysis of energy and area efficiency in various memory technologies, we argue that without a re-evaluation of memory organization, digital neuromorphic processors may struggle to compete effectively in edge and embedded applications. We conclude with potential pathways for future research to overcome the limitations of on-chip memory in neuromorphic systems.