qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking

TL;DR

This paper introduces a frequency-aware post-routing optimization framework for AQFP circuits with delay line clocking, improving timing closure and reducing buffer overhead while balancing performance and latency.

Contribution

It presents a novel optimization method that jointly considers clock period, latency, and timing slack, addressing limitations of fixed timing parameters in AQFP design.

Findings

Achieved 100% post-routing timing closure across various benchmarks.

Reduced phase-skipping buffer insertion by 34% on average.

Only decreased operating frequency by 4% while optimizing performance-latency trade-offs.

Abstract

Adiabatic Quantum-Flux-Parametron (AQFP) logic is an ultra-low-power superconducting logic family with energy consumption approaching the Shannon limit, making it attractive for quantum computing control and cryogenic computing systems. Traditional AQFP designs face significant physical design challenges due to strict gate-level clocking requirements and limited interconnect lengths, leading to substantial buffer overhead and difficult timing closure. Recently, delay-line clocking of AQFP has been proposed to improve timing margins and reduce latency by enabling more flexible clock scheduling. However, prior work has primarily focused on placement and latency minimization, while relying on fixed timing parameters that do not capture the frequency dependence of AQFP setup and hold constraints. To address this limitation, we propose a frequency-aware post-routing optimization framework that jointly optimizes clock period, latency, and timing slack under user-specified weighting. Experimental results across common benchmarks achieve 100% post-routing timing closure across a range of performance--latency--slack trade-offs. Our approach also automates phase-skipping, reducing path-balancing buffer insertion by 34% on average while only reducing operating frequency by 4%.