Behavioral-Level Simulation of Digital Readout for COFFEE at LHCb Upstream Pixel Tracker

TL;DR

This paper presents detailed digital readout simulation results for the COFFEE pixel sensor, demonstrating high efficiency and resource evaluation to guide its design for the LHCb Upstream Pixel Tracker upgrade.

Contribution

It provides the first detailed simulation analysis of COFFEE's digital readout circuitry, including efficiency and resource requirements, for high-rate particle detection.

Findings

Column-drain readout achieves nearly 100% efficiency at 100 ns cycle

Buffer depth and memory resources are evaluated for the data format

Simulation guides the design of COFFEE and its variants in upcoming fabrication

Abstract

COFFEE series is a HVCMOS pixel sensor using the advanced 55 nm process, currently being developed for the Upstream Pixel (UP) tracker of the LHCb Upgrade II. To ensure that COFFEE will be able to handle the particle hit rates at UP tracker, which reach a maximum of 322.5 MHz/chip, detailed simulation of the digital readout circuitry was performed. Simulation results show that the column-drain readout mechanism achieves nearly 100\% efficiency when the single readout cycle does not exceed 100 ns. Meanwhile, the buffer depth and memory resources required for the peripheral readout adapted to the BXID-sharing data format are also evaluated. These provide guidance for the design of COFFEE. The column-drain readout mechanism was used in COFFEE3 (fabricated in 2025), while the peripheral readout architecture adapted to the BXID-sharing data format is implemented in CHiR (taped out in early 2026).