Symbolic Polyhedral-Based Energy Analysis for Nested Loop Programs

TL;DR

This paper introduces a symbolic energy analysis method for nested loop programs on parallel processor arrays, enabling scalable and design-aware energy estimation without simulation.

Contribution

It provides a scalable symbolic approach that captures mapping and scheduling impacts on energy consumption, outperforming traditional simulation methods in size and efficiency.

Findings

The symbolic analysis is independent of iteration space size.

It accurately compares energy consumption across different mappings.

The method aids in design space exploration and architecture comparison.

Abstract

This work presents a symbolic approach for estimating the energy consumption for nested loop programs when mapped and scheduled on parallel processor array accelerator architectures. Instead of simulation-based evaluation, we derive a methodology for symbolic energy analysis that captures the impact of mapping and scheduling decisions of loop nests on processor arrays. We compare our approach against simulation-based results for selected benchmarks and varying sizes of the iteration spaces. Whereas the latter are not scalable, our symbolic analysis is shown to be independent of the problem size. The presented evaluation methodology can be beneficially used during the design space exploration of mapping and scheduling decisions, for studying the influence of array size variations, and for comparisons with other loop nest accelerator architectures.