CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations

TL;DR

CoverAssert is an iterative framework that enhances LLM-generated SystemVerilog assertions by leveraging functional coverage feedback, significantly improving coverage metrics in hardware design verification.

Contribution

It introduces an iterative, coverage-driven approach that clusters semantic and structural features to guide LLM assertion generation, improving coverage in hardware verification.

Findings

Average 9.57% improvement in branch coverage

Average 9.64% improvement in statement coverage

Average 15.69% improvement in toggle coverage

Abstract

LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.