TL;DR
This paper introduces PTE, a new hardware-aware efficiency metric for Tool-Integrated Reasoning that better correlates with actual latency and reveals inefficiency patterns affecting reasoning quality.
Contribution
It proposes PTE as a comprehensive metric for TIR efficiency, validated in industrial settings, and uncovers key inefficiency patterns impacting reasoning performance.
Findings
PTE correlates better with wall-clock latency than token counts.
Four inefficiency patterns are identified in TIR workflows.
Higher PTE costs are associated with lower reasoning correctness.
Abstract
In real-world Tool-Integrated Reasoning (TIR) scenarios, where LLMs interleave reasoning with external tool calls, a major source of inefficiency is that the toolcalls create pauses between LLM requests and cause KV-Cache eviction, forcing recomputation. Also, the long, unfiltered response returned by external tools inflates the KV-Cache, so each decode step spends more time loading the growing cache and thus becomes steadily slower as context length increases. However, existing efficiency metrics like token counts and toolcall counts fail to capture the real model inference latency. To address this, we introduce PTE (Prefill Token Equivalents), a hardware-aware TIR-efficiency metric that unifies internal reasoning and external tool-use costs while explicitly accounting for non-reusable KV-Cache and long-tool-response scenarios. Validation in a high-concurrency industrial setting…
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