An Ultra-Low-Power Synthesizable Asynchronous AER Encoder for Neuromorphic Edge Devices

TL;DR

This paper introduces a fully synthesizable, asynchronous AER encoder for neuromorphic edge devices that achieves high throughput, low power consumption, and compatibility with standard digital design flows.

Contribution

It presents a novel tree-based asynchronous AER encoder design that is fully synthesizable and fabricated in 65 nm CMOS, enabling scalable neuromorphic systems.

Findings

Peak throughput of 33 MEvent/s demonstrated in silicon.

Average event latency measured at 50 ns.

Power consumption of 435 fJ per event.

Abstract

This paper presents a fully synthesizable, treebased Address-Event Representation (AER) encoder designed for scalable neuromorphic computing systems. To achieve high throughput while maintaining strict compatibility with commercial EDA workflows, the asynchronous design employs a bundled-data protocol within a semi-decoupled micropipeline. The architecture replaces traditional transparent latches with standard edge-triggered flip-flops, enabling digital synthesis and place-and-route (PnR) using Cadence toolkits. A cross-coupled NAND-based random-priority arbiter is embedded within the encoder of each tree node to resolve event collisions efficiently. An 8-event AER prototype is fabricated in 65 nm CMOS technology utilizing a purely digital standard-cell flow. Post-fabrication silicon measurements validate the design, demonstrating a peak throughput of 33 MEvent/s and an average event latency of 50 ns, equating to a propagation delay of 17 ns/(event-bit). The design consumes only 435 fJ per encoded event.