Lightweight True In-Pixel Encryption with FeFET Enabled Pixel Design for Secure Imaging
Md Rahatul Islam Udoy, Diego Ferrer, Wantong Li, Kai Ni, Sumeet Kumar Gupta, and Ahmedullah Aziz

TL;DR
This paper presents SecurePix, a CMOS-compatible pixel architecture that performs true in-pixel encryption using ferroelectric FETs, significantly enhancing security in imaging pipelines with low hardware overhead.
Contribution
Introducing SecurePix, a novel in-pixel encryption architecture utilizing ferroelectric FETs for secure imaging, simulated in HSPICE with demonstrated strong resistance to neural inference.
Findings
ResNet-18 accuracy drops from 99.29% to 9.58% on MNIST after encryption.
ResNet-18 accuracy drops from 91.33% to 6.98% on CIFAR-10 after encryption.
Per-pixel programming power-delay product is 17 uW us, sensing power-delay is 1.25 uW us.
Abstract
Ensuring end-to-end security in image sensors has become essential as visual data can be exposed through multiple stages of the imaging pipeline. Advanced protection requires encryption to occur before pixel values appear on any readout lines. This work introduces a secure pixel sensor (SecurePix), a compact CMOS-compatible pixel architecture that performs true in-pixel encryption using a symmetric key realized through programmable, non-volatile multidomain polarization states of a ferroelectric field-effect transistor. The pixel and array operations are designed and simulated in HSPICE, while a 45 nm CMOS process design kit is used for layout drawing. The resulting layout confirms a pixel pitch of 2.33 x 3.01 um^2. Each pixel's non-volatile programming level defines its analog transfer characteristic, enabling the photodiode voltage to be converted into an encrypted analog output…
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