A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM

TL;DR

This paper surveys power delivery challenges in DRAM-based compute-in-memory systems, analyzing current demand patterns and proposing mitigation strategies for scalable, reliable in-memory computing.

Contribution

It introduces a unified taxonomy for PIM-induced current behavior and analyzes how various PIM techniques stress the power delivery network, guiding future design improvements.

Findings

PIM techniques cause voltage droop, IR drop, and hotspots in DRAM systems.

Bursty activations and multi-row operations significantly stress the power delivery network.

Architectural and circuit-level mitigation strategies can improve PIM system reliability.

Abstract

Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing ecosystem, and compatibility with existing systems. Recent works exploit multiple levels of the DRAM hierarchy - including subarrays, banks, and 3D-stacked organizations - to enable in-memory computation using mechanisms such as multi-row activation, row-buffer operations, and near-bank compute units. However, these approaches introduce non-traditional current demand patterns that challenge the power delivery network (PDN). This paper surveys PDN challenges in DRAM-based PIM systems and proposes a unified taxonomy that characterizes PIM-induced current behavior along temporal (burst vs. sustained) and spatial (localized vs. distributed) dimensions. Using this framework, we analyze how representative PIM techniques stress the PDN through bursty activations, multi-row concurrency, and large-scale parallel execution, leading to voltage droop, IR drop, and thermal hotspots. We further discuss DRAM-specific mitigation strategies leveraging existing architectural and circuit-level mechanisms, including timing constraints, memory controller scheduling, data placement, and bank- and vault-level power management. This survey highlights the importance of PDN-aware design for scalable and reliable DRAM-based PIM systems and outlines key future research directions.