Mestra: Exploring Migration on Virtualized CGRAs

TL;DR

Mestra introduces a system for multi-tenant CGRAs that enables dynamic scheduling and live migration, significantly improving hardware utilization and workload performance on FPGA-based CGRAs.

Contribution

It presents Mestra, a novel end-to-end system supporting live kernel migration and dynamic resource allocation for multi-tenant CGRAs, addressing fabric fragmentation issues.

Findings

Workload makespan improved by up to 70.48% with spatial sharing.

Tail latency reduced by up to 29.60% through live kernel migration.

Hardware overhead for virtualization is minimal, at 0.13% LUT per region.

Abstract

As modern Coarse Grain Reconfigurable Arrays (CGRAs) grow in size, efficient utilization of the available fabric by a single application becomes increasingly difficult. Existing CGRA mappers either fail to utilize the available fabric or rely on rigid static code transformations with limited adaptability. Multi-tenant CGRAs have emerged as a promising solution to increase hardware utilization, but current attempts fail to address key challenges such as fabric fragmentation and live migration. To address this gap, we present Mestra, an end-to-end system for CGRA multi-tenancy that supports dynamic scheduling and resource allocation in a shared environment. Mestra addresses fabric fragmentation caused by kernels completing out of order by supporting both stateless and stateful live kernel migration as a de-fragmentation mechanism. We assess our solution on an Alveo-U280 data-center-grade FPGA card, reporting area, frequency, and power. Performance is evaluated using routines from the PolyBench benchmark suite and kernels derived from common machine learning operators. Results show that spatial sharing of the available fabric across multiple users improves workload makespan by up to 70.48%, while live kernel migration reduces tail latency on fragmented layouts by up to 29.60%. The custom tightly coupled controller and read-back paths required for virtualization and stateful migration introduce a LUT cost of 0.13% per region. Our evaluation reveals that multi-tenancy is important for efficient CGRA utilization, and live kernel migration can further improve performance by recovering fragmented space with minimal hardware cost.