Area Optimization of Open-Source Low-Power INA in 130nm CMOS using Hybrid Mixed-Variable PSO

TL;DR

This paper introduces an open-source optimization framework using hybrid mixed-variable PSO and gm/ID methodology to significantly reduce the silicon area of analog circuits, exemplified by a low-power instrumentation amplifier.

Contribution

It presents a novel open-source framework combining hybrid mixed-variable PSO and gm/ID for area optimization in analog circuit design.

Findings

Achieved 90.33% reduction in gate area for a low-power instrumentation amplifier.

Demonstrated effectiveness of the framework in minimizing layout area while meeting design specs.

Abstract

As open-source silicon initiatives democratize access to integrated circuit development using multi-project environments, silicon area has become a premium resource. However, minimizing this layout area traditionally forces designers to compromise on core performance specifications. To address this challenge, this paper presents an open-source framework based on a hybrid mixed-variable particle swarm optimization algorithm and the gm/ID methodology to minimize the layout area of complex analog circuits while meeting design requirements. The framework's efficacy is demonstrated by designing a low-power instrumentation amplifier that achieves a 90.33% reduction in gate area over existing implementations.