Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension

TL;DR

This paper introduces a hardware extension that allows real-time processors to deliver user-level interrupts deterministically and with bounded latency, improving security and performance for critical embedded systems.

Contribution

A novel hardware extension enabling direct, deterministic user-level interrupt delivery without kernel intervention, significantly reducing worst-case latency in real-time processors.

Findings

Reduces worst-case latency by over 50x

Increases core area by 19% (2% of total die area)

Increases dynamic power by 4.1%

Abstract

The growing complexity of real-time embedded systems demands strong isolation of software components into separate protection domains to reduce attack surfaces and limit fault propagation. However, application-supplied device interrupt handlers -- even untrusted -- have to remain in the kernel to minimize interrupt latency, undermining security and burdening manual certifications. Current hardware extensions accelerate interrupts only when the target protection domain is scheduled by the kernel; consequently, they are limited to improving average-case performance but not worst-case latency, and do not meet the requirements of critical real-time applications such as autonomous vehicles or robots. To overcome this limitation, we propose a novel hardware extension that enables direct, deterministic switching to the appropriate protection domain upon user-level interrupt arrival -- without kernel intervention -- even when that domain is dormant. Our hardware extension reduces worst-case latency by more than 50x with a 19% increase in core area (2% of total die area) and 4.1% increase in dynamic power. To the best of our knowledge, this is the first integrated mechanism to guarantee user-level interrupt delivery with a nanosecond-scale yet bounded worst-case latency.