EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring

TL;DR

EEspice is an open-source circuit simulation platform that uses graph coloring to enable parallel device model evaluation, significantly accelerating simulations on multi-core systems.

Contribution

The paper introduces EEspice, a modular simulation framework that decouples device evaluation and employs graph coloring for parallel processing, overcoming bottlenecks in traditional SPICE simulators.

Findings

Achieves up to 45x speedup on a 64-core workstation.

Parallel device evaluation reduces simulation bottlenecks.

Performance depends on circuit topology and conflict levels.

Abstract

As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurate high-performance simulators have become an indispensable foundation for modern integrated circuit (IC) design. However, the computational cost of evaluating nonlinear models, particularly for BSIM models, remains a significant bottleneck. In standard parallelization approaches, devices such as transistors are easily distributed across processors. The subsequent stamping phase, where each device's contributions are added to the shared system matrix, often creates a bottleneck. Because multiple processor cores compete to update the same matrix elements simultaneously, the system is forced to process tasks one at a time to avoid errors. This paper introduces EEspice, an open-source circuit simulation framework whose modular architecture decouples device model evaluation into independently replaceable kernels, enabling a parallel stamping strategy that overcomes this bottleneck. It partitions MOSFET instances into independent color groups, which can be processed in parallel. Our results show that on a 64-core workstation, the proposed approach achieves up to 45x speedup over single-thread performance when conflicts are low. Our analysis also explores how performance depends on circuit topology.