Escaping Flatland: A Placement Flow for Enabling 3D FPGAs

TL;DR

This paper presents a specialized placement flow for 3D FPGAs that enhances timing and routing efficiency by addressing the unique challenges of 3D architectures, outperforming existing tools.

Contribution

The authors develop a novel 3D FPGA placement flow with integrated partitioning, adaptive scheduling, and delay estimation, tailored for 3D FPGA architectures.

Findings

Achieved up to 18% reduction in critical-path delay on 3D FPGA architectures.

Reduced routed wirelength by up to 10% compared to VTR.

Improved timing estimates and layer assignment exploration in 3D FPGA placement.

Abstract

3D field-programmable gate arrays (FPGAs) promise higher performance through vertical integration. However, existing placement tools, largely inherited from 2D frameworks, fail to capture the unique delay characteristics and optimization dynamics of 3D fabrics. We introduce a 3D FPGA placement flow that integrates partitioning-based initialization, adaptive cost scheduling, refined delay estimation, and a simulated annealing move set -- all targeted at 3D FPGA architecture. Together, these enhancements improve timing estimates and the exploration of layer assignments during placement. Compared to Verilog-To-Routing (VTR), our experiments show geometric-mean (max) critical-path delay reductions of ~3% (~7%), ~2% (~4%), ~3% (~8%), and ~6% (~18%) for four 3D architectures: 3D CB, 3D CB-O, 3D CB-I, and 3D SB, respectively. We also achieve geometric-mean (max) routed wirelength reductions of ~1% (~3%), ~2% (~8%), < 1% (~5%), and ~5% (~10%), respectively. Our work will be permissively open-sourced on GitHub.