Integer-State Dynamics of Quantized Spiking Neural Networks for Efficient Hardware Acceleration

TL;DR

This paper models quantized spiking neural networks as integer dynamical systems to understand how finite-precision effects influence network behavior and hardware efficiency.

Contribution

It introduces an integer-state dynamical framework for hardware-oriented SNNs, emphasizing the role of numerical precision as a design variable.

Findings

Bounded and recurrent temporal structures observed in simulations.

Quantization sensitivity significantly affects network regimes.

Representation semantics and scaling choices heavily influence dynamics.

Abstract

Spiking neural networks (SNNs) support energy-efficient machine intelligence because event-driven computation and sparse activity map naturally to low-power digital hardware. In practical implementations, however, membrane states, synaptic weights, and thresholds are represented with finite-precision integer arithmetic. Quantization, clipping, and overflow can therefore alter network dynamics, not just approximate a higher-precision model. This paper adopts an integer-state dynamical perspective, modeling a hardware-oriented SNN as a deterministic map on a bounded integer lattice. Under this view, recurrence, periodic orbits, and regime changes become intrinsic properties of the system. We introduce a lightweight update rule with integer-valued states and shift-based leakage, and demonstrate the approach through exploratory simulations with network sizes N = 30-130, connection densities 0.1-0.9, and bit widths 4/8/16 over T = 1000 steps. The results show bounded and recurrent temporal structure with strong quantization sensitivity. The observed regimes depend heavily on representation semantics and scaling choices. These findings suggest that numerical precision acts as a dynamical design variable and highlight integer-state analysis as a useful framework for hardware-aware SNN co-design, motivating future work on attractor analysis, precision-aware training, and FPGA/ASIC validation.