Geometry-induced correlated noise in qLDPC syndrome extraction

TL;DR

This paper investigates how the physical geometry of quantum circuits influences correlated noise in syndrome extraction, deriving theoretical models and demonstrating that optimized layouts can significantly reduce logical error rates.

Contribution

It introduces a geometry-conditioned interaction model for correlated faults and shows that layout optimization can suppress error rates in quantum error correction.

Findings

Geometry layout affects residual coupling and correlated noise.

A biplanar layout reduces geometry penalty compared to a single-plane layout.

Optimized embeddings decrease logical error rates by over 26%.

Abstract

Routed geometry is a device-level choice in a fixed syndrome-extraction circuit. Two embeddings of the same code can set different physical separations between gate blocks active in the same time step, and these separations control the residual coupling between those blocks. We derive how this choice shapes the leading correlated-fault structure of the effective data channel, and we test the consequences at circuit level. Starting from a geometry-conditioned interaction Hamiltonian on disjoint blocks within one tick, we obtain a retained data channel of single and pair faults for bivariate-bicycle codes, with a truncation error controlled by the per-tick coupling strength. Two geometry metrics emerge. In the combinatorial limit, a matching argument on the logical support reduces the effective fault weight on that support. For strictly positive kernels, once every support pair contributes somewhere in the schedule, the induced support graph becomes complete. At that point the matching-number reduction is exhausted, and the embedding-dependent quantity is the total retained pair weight on the support, which we call the weighted exposure. Circuit-level Monte Carlo on the $[\![72,12,6]\!]$ and $[\![144,12,12]\!]$ benchmarks shows that a biplanar layout, with the schedule split across two routing planes, suppresses the geometry penalty incurred by the monomial layout in a single plane. On the BB72 baseline set of $101$ operating points, the reference-support weighted exposure is strongly correlated with the observed logical error rate (Spearman $\rho_\mathrm{S}=0.893$) in the tested window. A logical-aware two-swap local search over single-layer embeddings on BB72 reduces the worst-case family exposure by $26.11\%$ and lowers the logical error rate across the tested power-law window.