Quantum Non-Moduler Multiplication with QFT-Based Multi Input Parallelized Adder

TL;DR

This paper introduces a resource-efficient quantum multiplication method using a QFT-assisted parallel adder, reducing gate count and circuit complexity for quantum arithmetic operations.

Contribution

It presents a novel QFT-based multiplication approach that eliminates repeated QFT/IQFT operations, improving efficiency over traditional methods.

Findings

Design of a 3-bit quantum multiplier circuit validated on IBM simulators

Significant reduction in gate count and circuit depth achieved

Demonstrates feasibility of resource-efficient quantum multiplication

Abstract

In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.