A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems

TL;DR

This paper investigates how FPGA-based TDC nonlinearity impacts quantum key distribution performance and proposes mitigation strategies to improve timing accuracy and secret key rate.

Contribution

It introduces a system-level model linking TDC nonlinearity to QKD metrics and presents fabric-level mitigation methods to reduce nonlinearity effects.

Findings

Reductions of 14%-21% in INL with mitigation strategies.

Decreased QBER contribution improves secret fraction by 3.7%-14.2%.

Fabric-level delay shaping effectively reduces severe bin-width irregularities.

Abstract

Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.