HPCCFA: Leveraging Hardware Performance Counters for Control Flow Attestation

TL;DR

This paper introduces HPCCFA, a hardware-assisted control flow attestation method leveraging performance counters on commodity CPUs to detect runtime attacks in Trusted Execution Environments, demonstrated on RISC-V.

Contribution

It presents a novel approach using hardware performance counters for control flow attestation, extending TEEs to prevent runtime exploits.

Findings

Feasibility demonstrated on Keystone RISC-V implementation

Trade-off identified between detection reliability and performance overhead

Hardware-backed trace generation enables effective control flow monitoring

Abstract

Trusted Execution Environments (TEEs) allow the secure execution of code on remote systems without the need to trust their operators. They use static attestation as a central mechanism for establishing trust, allowing remote parties to verify that their code is executed unmodified in an isolated environment. However, this form of attestation does not cover runtime attacks, where an attacker exploits vulnerabilities in the software inside the TEE. Control Flow Attestation (CFA), a form of runtime attestation, is designed to detect such attacks. In this work, we present a method to extend TEEs with CFA and discuss how it can prevent exploitation in the event of detected control flow violations. Furthermore, we introduce HPCCFA, a mechanism that uses HPCs for CFA purposes, enabling hardware-backed trace generation on commodity CPUs. We demonstrate the feasibility of HPCCFA on a proof-of-concept implementation for Keystone on RISC-V. Our evaluation investigates the interplay of the number of measurement points and runtime protection, and reveals a trade-off between detection reliability and performance overhead.