CXLRAMSim v1.0: System-Level Exploration of CXL Memory Expander Cards

TL;DR

CXLRAMSim is a high-fidelity, gem5-integrated simulator that accurately models CXL memory expanders at the system level, enabling realistic simulation of large-scale memory systems for LLM workloads.

Contribution

It introduces CXLRAMSim, the first full-system simulator with accurate CXL device modeling integrated into gem5, improving simulation fidelity for CXL-based architectures.

Findings

Provides realistic latency-bandwidth behavior for CXL devices.

Enables use of unmodified Linux kernels and software stacks.

Captures cache pollution issues in CXL memory access.

Abstract

The growing demands in the training and inference of Large Language Models (LLMs) are accelerating the adoption of scale-up systems that extend server shared memory through the use of Compute Express Link (CXL)-based load/store interconnects. Accurate full-system simulation of such architectures remains challenging, as existing tools (all very recent) rely on simplified or non-compliant architectural models, impacting accuracy and usability. We present CXLRAMSim, the first gem5-integrated, full-system simulator that models CXL devices at their correct position on the I/O bus, enabling the use of unmodified Linux kernels and software stack, realistic latency-bandwidth behavior and true interleaving with system DRAM. Our approach provides high-fidelity CXL.mem characterization and captures key challenges such as cache pollution when accessing CXL memory.