ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning

TL;DR

ARCS is a fast, reinforcement learning-based system for generating valid analog circuit designs with high simulation success rates, significantly reducing computation time compared to traditional methods.

Contribution

The paper introduces ARCS, combining graph VAEs, flow models, and a novel multi-topology RL algorithm (GRPO) for efficient, valid circuit synthesis with guaranteed structural correctness.

Findings

Achieves 99.9% simulation validity across 32 topologies with only 8 SPICE evaluations.

Reaches 85% validity in 97ms for single-model inference, 600x faster than random search.

GRPO improves validity by +9.6 percentage points over REINFORCE in 500 RL steps.

Abstract

This paper presents ARCS (Autoregressive Circuit Synthesis), a system for amortized analog circuit generation. ARCS produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combines two learned generators, a graph VAE and a flow-matching model, with SPICE-based ranking. It achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution adapts Group Relative Policy Optimization (GRPO) to multi-topology circuit reinforcement learning. GRPO resolves a critical failure mode of REINFORCE, cross-topology reward distribution mismatch, through per-topology advantage normalization. This improves simulation validity by +9.6 percentage points over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking.