Toward a Universal GPU Instruction Set Architecture: A Cross-Vendor Analysis of Hardware-Invariant Computational Primitives in Parallel Processors

TL;DR

This paper conducts a comprehensive cross-vendor analysis of GPU instruction set architectures, identifying hardware-invariant primitives and proposing a vendor-neutral abstract execution model validated across multiple platforms.

Contribution

It is the first systematic analysis across all major GPU vendors, revealing invariant primitives, divergences, and proposing a universal GPU instruction set architecture model.

Findings

Identified ten hardware-invariant computational primitives across all four vendors.

Proposed a vendor-neutral abstract execution model for GPU ISA.

Validated the model with benchmark results on NVIDIA T4 and Apple M1, achieving comparable or better performance.

Abstract

We present the first systematic cross-vendor analysis of GPU instruction set architectures spanning all four major GPU vendors: NVIDIA (PTX ISA v1.0 through v9.2, Fermi through Blackwell), AMD (RDNA 1 to 4 and CDNA 1 to 4), Intel (Gen11, Xe-LP, Xe-HPG, Xe-HPC), and Apple (G13, reverse-engineered). Drawing on official ISA reference manuals, architecture whitepapers, patent filings, and community reverse-engineering efforts totaling over 5,000 pages of primary sources across 16 distinct microarchitectures, we identify ten hardware-invariant computational primitives that appear across all four architectures, six parameterizable dialects where vendors implement identical concepts with different parameters, and six true architectural divergences representing fundamental design disagreements. Based on this analysis, we propose an abstract execution model for a vendor-neutral GPU ISA grounded in the physical constraints of parallel computation. We validate our model with benchmark results on NVIDIA T4 and Apple M1 hardware, the two most architecturally distant platforms in our study. On five of six benchmark-platform pairs, the abstract model matches or exceeds native vendor-optimized performance. The single outlier (parallel reduction on NVIDIA, 62.5% of native) reveals that intra-wave shuffle must be a mandatory primitive, a finding that refines our proposed model.