Loop Control Management in Tightly Coupled Processor Arrays (TCPAs)

TL;DR

This paper presents a novel method to significantly reduce control overhead in TCPAs by deriving control conditions from polyhedral representations, enabling zero-overhead loop control.

Contribution

It introduces a polyhedral-based approach to derive and minimize control signals, along with a lightweight global controller architecture for TCPAs.

Findings

Achieved 15x to 45x reduction in control signals across benchmarks.

Control flow consumes less than 10% of total array resources.

Proposed architecture evaluates control conditions with hardware comparable to a single processing element.

Abstract

Multidimensional loop kernels often suffer from control overhead that can dominate execution time on parallel loop accelerators. Tightly Coupled Processor Arrays (TCPAs) offload loop control to a global controller (GC), but existing approaches still require hundreds of control signals. We propose a method to derive and aggressively reduce these control conditions from a polyhedral representation of the iteration space, achieving reductions of 15x to 45x in control signals across several benchmarks. We introduce a lightweight GC architecture that evaluates conditions as unions of polyhedra using bounded evaluation units, requiring hardware comparable to a single processing element. Control signals are distributed throughout the array with a minimal number of delay elements resulting in zero-overhead loop control. Our evaluation on PolyBench kernels shows that the entire control flow requires < 10 % of the total array resources.