Resonant-enhanced tunneling electroresistance in sliding ferroelectric tunnel junctions

TL;DR

This paper introduces a resonant tunneling mechanism in sliding ferroelectric tunnel junctions, significantly enhancing resistance contrast and enabling fast, low-energy, multistate memory devices at atomic scales.

Contribution

It demonstrates a novel resonant tunneling approach that greatly improves tunneling electroresistance in sliding ferroelectric devices, advancing nonvolatile memory technology.

Findings

Achieved a TER ratio of up to 225.65%.

Device exhibits fast switching at 20 ns and low energy consumption.

Demonstrated high endurance and multistate programmability.

Abstract

The escalating demand for memory scaling requires switching mechanisms that remain reliable at atomic thickness while operating with minimal energy consumption. Sliding ferroelectricity provides a promising platform for this challenge: the spontaneous interfacial polarization emerging at superlubric, atomically thin van der Waals interfaces endows exceptional fatigue resistance, ultrafast switching and ultralow coercive fields. Nevertheless, the intrinsically weak polarization of sliding ferroelectrics limits the available signal window, necessitating new physical mechanisms that can transduce subtle polarization variations into pronounced resistance contrasts. Here, we address this challenge by introducing momentum-conserving resonant tunneling between lattice-aligned graphene electrodes. The resulting resonant sliding ferroelectric tunnel junction achieves a tunneling electroresistance (TER) ratio of up to 225.65%, substantially exceeding that of conventional sliding ferroelectric tunnel junctions. In addition, the device delivers a tunable TER ratio, multistate programmability, high current density, robust endurance with a small coefficient of variation (<0.69%), fast switching (20 ns), low switching energy (310 fJ), and low read voltage (<0.2 V). Collectively, these results establish a unique role for sliding ferroelectricity in bridging the gap of memory technology between performance and miniaturization, and open a new pathway toward next-generation nonvolatile memory technologies.